1. Field of the Invention
This invention relates to the field of data processing. In particular, the invention relates to dynamic scheduling of instructions in a data processing apparatus.
2. Description of the Prior Art
Processors that employ dynamic scheduling and out-of-order execution techniques are known. In such processors, instructions are queued and dynamically selected for issue once their source operands have become available for processing. This involves identifying source operands, performing register renaming in order to avoid data hazards, queuing the instructions, updating instruction status as individual results from preceding instructions are produced, selecting one or more instructions from the queue to issue for execution and controlling forwarding of results between pipelined instructions. Instructions are not issued until the values of all their source operands have become available for processing. Sometimes issuing of an instruction has to be delayed for several processing cycles while a preceding instruction calculates a value of an operand. This reduces the processing speed of the processor.
Some in-order processors use scoreboard-based scheduling techniques to reduce the delay. Some instructions are executed in multiple processing cycles by a sequence of execute pipeline stages, and may not require some operands to be available until one of the later stages. If, for example, a particular operand is not needed until the Nth cycle then the instruction could be issued such that execution begins N cycles before the result is predicted to be produced by a preceding instruction. Scoreboard-based scheduling requires the system to monitor a large amount of state information associated with pending instructions and would require additional hardware for tracking both the progress of an instruction being executed and the availability of results of preceding instructions. This complex circuitry would not be practical in out-of-order processors, since the number of currently pending instructions which need to be monitored is much larger than for an in-order processor. The present invention seeks to provide a way of reducing scheduling latency without requiring this additional complexity.